Although it can in principle be applied to any desired integrated circuits, the present invention and the problem on which it is based are explained with reference to integrated memory circuits in silicon technology.
When fabricating integrated circuits, in particular integrated semiconductor memory circuits, it is necessary to produce various types of contacts. In this context, it is desirable for these various contacts to be produced with the smallest possible number of lithography levels and etching steps, in order to ensure high alignment accuracy and low costs.
A critical contact type which makes electrical contact with the active area between two adjacent gate stacks has to be provided between the gate stacks of an integrated semiconductor memory circuits, since the spacing of the gate stacks has a critical dimension. The contact hole for the critical contact is usually etched separately from other, less critical contacts.
For a number of technology generations, the search for a suitable CB contact hole etch (SAC etch=self-aligned contact) has been a central problem. The most important requirements include:                that short circuits should not be caused between bit line and word line (CB-GC shorts), i.e. the etch should be as selective as possible with respect to the silicon nitride; and        the CD dimension in the upper section of the contact hole should not be widened, since even slight widening would greatly increase the risk of CB—CB shorts via poorly aligned metalization tracks.        
Hitherto, the etching process has been realized by a two-stage etch. In the first step, etching is carried out as far as possible perpendicularly and anisotropically as far as the silicon nitride cap, and in the second step, etching is carried out as far as possible selectively with respect to the silicon nitride cap, the intention being that the profile of the upper region of the contact hole KB should as far as possible not be widened.
The problem on which the present invention is based consists in the fact that during the side wall oxidation of a gate stack having, for example, a lower polysilicon layer and a metal silicide layer above it, excessive oxidation of the metal silicide layer occurs. The protrusions formed in this way mean that CB–-GC short circuits may occur during the critical contact hole etch if the nitride cap is etched through and then the side wall oxide below it is removed.